2288H V5: CPU1/2 QPI/UPI Link-Failed Case

Source symptoms

A 2288H V5 reports CPU1/CPU2 configuration errors and CPU1/CPU2 QPI/UPI link-failed events in SEL:

FDM evidence in the case

The author interprets the broader FDM analysis as pointing toward CPU2, reported through CPU1, with a watchdog three-strike-timeout event. The illustrated entry itself says CPU:0 (Socket:CPU1); it is retained and must not be relabeled as proof that CPU2 is the failing FRU.

This English illustration reproduces the upper diagnostic pane: MCACODE0X0400, MSCODE0X0080, error 2/62, MCA Bank3(MLC), Core 1 and the original 2022-12-03 19:12:21 time. The original lower pane’s nonessential local case directory is replaced with a placeholder below. All 16 visible search results are stored as selectable text; 48 is the total search-hit count, not the number visible in the crop.

Search "MCACODE: 0X0400" (48 hits in 1 file)
<CASE_DIRECTORY>\dump_info\LogDump\FDMDecoder\fdm_log (48 hits)
Line 14: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 49: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 88: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 116: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 154: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 189: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 258: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 297: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 334: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 371: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 408: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 445: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 482: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 519: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 556: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)
Line 593: MCACODE: 0X0400 (Watchdog Timer(3-strike timeout) Error)

The source’s explanation that a cache-miss transaction times out is an abbreviated case explanation. A normal L1/L2 cache miss alone does not establish this catastrophic watchdog error or a specific defective component.

Diagnostic completion and alarm behavior

The source describes a CATERR/BMC diagnostic mechanism: after successful diagnosis, SEL reports an alarm and BMC waits for a subsequent rst_out trigger; after reboot the displayed alarm can disappear and later recur. It also states that a failed diagnosis can lead to an OS reset. These are attributed case/firmware behaviors, not a universal specification of every BMC reset/alarm path.

An alarm disappearing after reboot is not proof that a hardware fault was repaired. Preserve SEL/FDM/OS evidence and correlate the actual machine’s error sequence. The source recommends replacing CPU2 and the motherboard for its incident; obtain the vendor’s confirmed FRU diagnosis and matching service procedure before applying that recommendation elsewhere.