Lenovo SN550 FPGA Power Fault Interpretation
SN550 shows SEL > "Sensor SysBrd Vol Fault has transitioned to critical from a less severe state." For the SN550 a method to determine the source of a faulty voltage reported for a voltage planar fault is to look in the captured FFDC in the log parser detailed data. Locate the FPGA dump shown under the FPGA Diagnosis.
Here is a sample file from the ffdc parser:
System utility Ver 0.22 to dump FPGA registers run on Monday, June 07 2021
02:47 PM local time.
Platform id 0x56, name is Ventura
FPGA Version 4.08 [OFFICIAL_BUILD] 08-14-20
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Dump of Local Blocks
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Block 00 - 56 04 08 00 08 14 20 20 - 00 45 40 11 05 75 F9 00
Block 01 - 00 00 00 4E 00 00 00 56 - 00 07 00 00 00 00 00 06
Block 02 - A6 00 04 00 01 00 00 00 - 00 00 FF 00 00 00 00 00
Block 03 - 00 00 B7 00 03 00 83 00 - 00 FF 92 00 00 0C 00 00
Block 04 - 7F 40 00 00 40 00 00 00 - 00 01 27 80 80 01 20 00
Block 05 - 01 40 00 00 40 00 00 00 - 00 00 00 00 00 00 00 00
Block 06 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
Block 07 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
Block 08 - 81 2B 2F 32 02 15 10 40 - 50 60 51 00 10 1A 00 00Check the FPGA Version is 4.07 or greater.
If FPGA rev 4.7 or greater refer to table1.
If FPGA rev is less than 4.7 refer to table2.
Block 4 contains the power fault register content. For this example, the Block 04 registers are indicating source of fault is PGD_MAIN_EFUSE(P_12V) and MEZZCARD1_PWRGOOD. This fault indicates that the main board’s 12v was tripped due to a fault on the slot1 expansion card. Remove the expansion card in slot 1 to check if the planar recovers. If planar does not recover, then both the adaptor and planar would need to be replaced. If planar powers on normally than only the adaptor needs to be replaced. FPGA firmware should always be updated to the latest available. The FPGA code is packaged as part of the XCC firmware releases and automatically applied during XCC firmware updates.
Block 00 offset 0 is always 0x56. Block 00 offset 1-2 is the FGPA revision# 04.08. Block 4 offset 1-7 contain the power fault registers. A '1' indicates a fault with the indicated signal.
Figure 1: Block 4 power faults for FPGA version 4.7 or greater.
| Bit | Power Faults 7 (63:56) – Offset 1h | Bit | Power Faults 3 (31:24) – Offset 5h |
|---|---|---|---|
| 0 | 5V_aux_pg | 0 | X |
| 1 | 1V1_AUX_PG | 1 | X |
| 2 | 1V2_AUX_PG | 2 | X |
| 3 | 1V8_PCH_AUX_PG | 3 | X |
| 4 | VNN_PCH_AUX_PG | 4 | X |
| 5 | 1V05_PCH_AUX_PG | 5 | X |
| 6 | PGD_MAIN_EFUSE(P_12V) | 6 | X |
| 7 | 5V_PG | 7 | X |
| Bit | Power Faults 6 (55:48) – Offset 2h | Bit | Power Faults 2 (23:16) – Offset 6h |
| 0 | 3v3_PG | 0 | X |
| 1 | VPP_CPU1_ABC_PG | 1 | X |
| 2 | VPP_CPU1_DEF_PG | 2 | X |
| 3 | VPP_CPU2_ABC_PG | 3 | X |
| 4 | VPP_CPU2_DEF_PG | 4 | X |
| 5 | VDDQ_CPU1_ABC_PG | 5 | X |
| 6 | VDDQ_CPU1_DEF_PG | 6 | X |
| 7 | VDDQ_CPU2_ABC_PG | 7 | X |
| Bit | Power Faults 5 (47:40) – Offset 3h | Bit | Power Faults 1 (15:8) – Offset 7h |
| 0 | VDDQ_CPU2_DEF_PG | 0 | X |
| 1 | VTT_CPU1_ABC_PG | 1 | X |
| 2 | VTT_CPU1_DEF_PG | 2 | X |
| 3 | VTT_CPU2_ABC_PG | 3 | X |
| 4 | VTT_CPU2_DEF_PG | 4 | X |
| 5 | CPU1_VCCIO_PG | 5 | X |
| 6 | CPU2_VCCIO_PG | 6 | X |
| 7 | VCCIN_CPU1_PG | 7 | X |
| Bit | Power Faults 4 (39:32) – Offset 4h | Bit | Power Faults 7 (7:0) – Offset 8h |
| 0 | VCCIN_CPU2_PG | 0 | X |
| 1 | VCCSA_CPU1_PG | 1 | X |
| 2 | VCCSA_CPU2_PG | 2 | X |
| 3 | PCH_CPU_PWRGD_3V | 3 | X |
| 4 | MEZZCARD1_AUX_PWRGOOD | 4 | X |
| 5 | MEZZCARD2_AUX_PWRGOOD | 5 | X |
| 6 | MEZZCARD1_PWRGOOD | 6 | X |
| 7 | MEZZCARD2_PWRGOOD | 7 | M2_ADAPTER_FAULT |
Figure 2: Block 4 power faults for FPGA version earlier than 4.7
| Bit | Power Faults 7 (63:56) – Offset 1h | Bit | Power Faults 3 (31:24) – Offset 5h |
|---|---|---|---|
| 0 | 5V_aux_pg | 0 | MEZZCARD1_PWRGOOD |
| 1 | 2V5_AUX_PG | 1 | X |
| 2 | 1V1_AUX_PG | 2 | X |
| 3 | 1V2_AUX_PG | 3 | X |
| 4 | 1V8_PCH_AUX_PG | 4 | X |
| 5 | VNN_PCH_AUX_PG | 5 | X |
| 6 | 1V05_PCH_AUX_PG | 6 | X |
| 7 | PGD_MAIN_EFUSE(P_12V) | 7 | X |
| Bit | Power Faults 6 (55:48) – Offset 2h | Bit | Power Faults 2 (23:16) – Offset 6h |
| 0 | 5V_PG | 0 | X |
| 1 | 3v3_PG | 1 | X |
| 2 | VPP_CPU1_ABC_PG | 2 | X |
| 3 | VPP_CPU1_DEF_PG | 3 | X |
| 4 | VPP_CPU2_ABC_PG | 4 | X |
| 5 | VPP_CPU2_DEF_PG | 5 | X |
| 6 | VDDQ_CPU1_ABC_PG | 6 | X |
| 7 | VDDQ_CPU1_DEF_PG | 7 | X |
| Bit | Power Faults 5 (47:40) – Offset 3h | Bit | Power Faults 1 (15:8) – Offset 7h |
| 0 | VDDQ_CPU2_ABC_PG | 0 | X |
| 1 | VDDQ_CPU2_DEF_PG | 1 | X |
| 2 | VTT_CPU1_ABC_PG | 2 | X |
| 3 | VTT_CPU1_DEF_PG | 3 | X |
| 4 | VTT_CPU2_ABC_PG | 4 | X |
| 5 | VTT_CPU2_DEF_PG | 5 | X |
| 6 | CPU1_VCCIO_PG | 6 | X |
| 7 | CPU2_VCCIO_PG | 7 | X |
| Bit | Power Faults 4 (39:32) – Offset 4h | Bit | Power Faults 7 (7:0) – Offset 8h |
| 0 | VCCIN_CPU1_PG | 0 | X |
| 1 | VCCIN_CPU2_PG | 1 | X |
| 2 | VCCSA_CPU1_PG | 2 | X |
| 3 | VCCSA_CPU2_PG | 3 | X |
| 4 | PCH_CPU_PWRGD_3V | 4 | X |
| 5 | MEZZCARD1_AUX_PWRGOOD | 5 | X |
| 6 | MEZZCARD2_AUX_PWRGOOD | 6 | X |
| 7 | MEZZCARD1_PWRGOOD | 7 | M2_ADAPTER_FAULT |